1. Field of the Invention
The present invention relates to microprocessor systems, and more particularly, to translation lookaside buffers for use in conjunction with high performance microprocessors.
2. Art Background
In order to avoid frequent, cycle consuming accesses of main memory, a microprocessor system frequently utilizes cache memory. Cache memory is typically comprised of a relatively small amount of static random access memory (SRAM) which is both physically faster than main memory and arranged such that it can be addressed more rapidly than main memory. The microprocessor within the system then uses the faster cache memory to capture and store processor information as it is used. The processor information is stored within the cache memory in accordance with a predetermined mapping policy. Examples of such mapping policies include, direct mapping, set associative mapping, and fully associative mapping. The storage of processor information in a cache memory allows the processor to quickly and advantageously obtain this information from the cache memory rather than from main memory. The intelligent design and use of a cache memory can substantially enhance the performance of the overall microprocessor system.
Modern microprocessor systems also typically utilize virtual addressing. Virtual addressing enables the system to effectively create a virtual memory space larger than the actual physical memory space. A processor can then advantageously operate in virtual address space using virtual addresses. Frequently, however, these virtual addresses must be translated into physical addresses. One way of accomplishing this translation of virtual addresses into physical addresses is to regularly access translation tables stored in main memory. However, regularly accessing translation tables in main memory tends to slow overall system performance. Accordingly, in order to avoid the need to regularly access translation tables in main memory to accomplish address translation, modern microprocessor systems often use a translation lookaside buffer (TLB) to store or cache recently generated virtual to physical address translations.
A translation lookaside buffer (TLB) can be thought of as a special type of cache memory. As with other types of caches, a TLB is typically comprised of a relatively small amount of memory specially designed to be quickly accessible. A TLB typically incorporates both a tag array and a data array. Within the tag array, each tag line stores a virtual address. This tag line is then associated with a corresponding data line in the data array which stores the physical address translation for the virtual address. Thus, prior to seeking a translation of a virtual address from translation tables in main memory, a processor can first refer to the TLB to determine whether the physical address translation of the virtual address is presently stored in the TLB. In the event that the virtual address and corresponding physical address are presently stored in the TLB, the TLB responsively outputs the corresponding physical address, and a time-consuming access of main memory is avoided.
A number of issues must be addressed in the design and operation of a TLB. One such issue is the mapping policy of the TLB. As noted above, a cache can be mapped in accordance with one of any number of mapping policies, including direct mapping, set associative mapping, and fully associative mapping. A TLB mapped in accordance with a fully associative mapping policy provides the advantage of operating at a greater speed than a similarly designed TLB mapped in accordance with a set associative mapping policy. However, a fully associative TLB will tend to require a greater amount of chip space to implement.
A second issue which arises is the issue of different page lengths. Under certain circumstances, it is desirable to use large pages sizes, while under other circumstances, it is desirable to use small page sizes. Page sizes, it will be appreciated, correspond to the organization of information in main memory. In a virtual memory system, when a processor wishes to access a particular location in main memory, it specifies both a virtual address for the page in main memory (which must be translated into a physical address for the page) and the address within that page. The desire to provide for the translation of virtual addresses corresponding to both a first page size and a second page size has typically led to designs which utilize two TLB's. A first TLB is used to store virtual address/physical address pairs for a first page size, while a second TLB is used to store virtual address/physical address pairs for a second page size.
As will be described, the present invention provides for a single, fully associative TLB capable of storing and managing virtual address/physical address pairs of varied page sizes. In particular, the TLB of the present invention incorporates control cells in the tag array, and control cells in conjunction with multiplexing data cells in the data array to directly manage tag lines and data lines of varied page sizes without slowing the speed path of the TLB.